Power vs. Delay in Gate Sizing: Connicting Objectives?
نویسندگان
چکیده
The problem of sizing gates for power-delay tradeo s is of great interest to designers. In this work, the theoretical basis for gate sizing under delay and power considerations is presented, and results on a practical implementation are presented. The dynamic power as well as the short-circuit power are modeled, using notions of delay and transition density, and the optimization problem is formulated using notions of convex programming. Previous approaches have not modeled the short circuit power, and our experimental results show that the incorporation of this leads to counter-intuitive results where the minimumpower circuit is not necessarily the minimum-sized circuit.
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